The present invention relates to the field of semiconductor processing and, more particularly, to the processing of semiconductors having wide metal wiring lines.
Generally, semiconductor devices include a plurality of integrated circuits (ICs). ICs can be useful for many applications including computers and electronic equipment and they can contain millions of transistors and other circuit elements that can be fabricated on a single semiconductor chip. For device functionality, a complex of signal paths will typically be routed to connect the circuit elements distributed on the surface of the semiconductor device. Efficient routing of these signals across the device can become more difficult as the complexity and number of ICs is increased. Thus, the formation of multi-level or multi-layered interconnect schemes have become more desirable due to their efficiency in providing high-speed signal routing patterns between a large number of transistors on a single semiconductor chip. The preferred interconnect metal is copper.
In fabricating IC wiring with a multi-level scheme, an insulating material (oftentimes referred to as a dielectric material) such as silicon dioxide (SiO2), will normally be patterned to provide trenches that are subsequently filled with conductive material to provide metal lines for electrical connectivity. Prior to the deposition of the conductive material, a conformal diffusion barrier, often referred as a liner, is formed along the base and sidewalls of the trench. Following the formation of the diffusion barrier, a metal, such as copper, is deposited within the trench and planarized to provide metal lines. The foregoing method of patterning and filling trenches is referred to as a single damascene process.
A dielectric layer is then blanket deposited atop the metal lines and the insulating material. The dielectric layer is then normally patterned to create openings for conductive lines and/or vias using photolithography and etching. A diffusion barrier (liner) is then formed along the sidewalls and the base of the via and a metal, such as copper, is deposited within the vias to be in electrical contact with the metal line, as discussed above. The diffusion barrier material typically comprises tantalum nitride and/or tantalum. The foregoing method of patterning and filling conductive lines and vias is referred to as a dual damascene process.
Copper, despite having a low resistance suitable for electrical connectivity in high-speed devices, is susceptible to electromigration. Contrary to copper, tantalum or tantalum nitride is substantially less susceptible to electromigration and serves as a barrier for copper diffusion.
Reliability of copper interconnects is usually limited by failure mechanisms such as electromigration (EM) and stress migration (SM). In EM, copper atoms migrate in the direction of the electron flow, eventually causing a void in the copper lines. In SM, copper atoms diffuse to relieve the thermal stress caused by the mismatch in the coefficient of thermal expansion (CTE) between the copper and the surrounding dielectric. Here, void formation is also possible if sufficient vacancies are available. For dual damascene processing, in which the vias and metal lines are formed in the same step, liner materials are used for improved yield and reliability. That is, if voids are present in the copper vias or metal lines, an open circuit is prevented by having a current path through the conductive liners. As noted above, these liner materials are typically tantalum nitride and/or tantalum.
Interconnect structures with a via landing on a wide metal line typically show the poorest EM reliability. In this case, the via fails to make contact with the tantalum-based liners of the metal line below. Once the EM induced void grows across the base of the via, no metallic liner exists that can act as a redundant pathway for the current and the structure electrically goes open. Hence, this structure shows a low median time to fail. The same problem exists for SM in which a single via lands on a large metal plate.
The EM and SM reliability of such structures are improved when the depth the via gouges into the line below is increased. The liner etchback process causes via gouging, where an argon sputter etch removes liner material from the bottom of the via and also etches into the metal line below the via. An increase in liner etchback produces more via gouging/recess into the underlying metal line. With gouging, the resulting larger contact area requires a larger void, and thus longer time, before the structure fails. Non-gouged vias have an interface under high tensile strain due to thermal stress. By gouging the via, the interface is enlarged, lowering the stress density and also partially transforming the tensile component into a shear component (flat surface versus arched surface). The yield strength for shear stress along the copper-tantalum-copper interface may be higher than for tensile stress, raising the threshold for SM failure. However, attempting to increase via gouging into the line below has drawbacks. Due to the dual damascene nature, the process of increasing via gouging removes liner from the bottom of the trench (or metal line) above the via. This results in additional reliability issues like time dependent dielectric breakdown (TDDB), especially with low dielectric constant (low-k) materials.
Yen et al. U.S. Pat. No. 6,686,279, Park et al. U.S. Pat. No. 6,884,710 and Mehta et al. U.S. Patent Application Publication US 2008/0012142, the disclosures of which are incorporated by reference herein, disclose gouging in general.
Nguyen et al. U.S. Pat. No. 7,138,714, the disclosure of which is incorporated by reference herein, discloses using dielectric fill shapes for improved EM reliability. However, Nguyen et al. pertains to a wide metal line below the via only. The dielectric fill shapes are placed in the line below the via so as to provide liner redundancy during EM testing. The main intention of Nguyen et al. is to make the via liner touch the liner of the metal line below, by either notching the line below or introducing dielectric islands in the line below. The dielectric fill shapes need to make contact with the via in order to obtain reliability benefits.